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april 2011 doc id 9302 rev 9 1/16 16 l6926 high efficiency monolithic synch ronous step down regulator features 2 v to 5.5 v battery input range high efficiency: up to 95% internal synchronous switch no external schottky required extremely low quiescent current 1 ma max shutdown supply current 800 ma max output current adjustable output voltage from 0.6 v low drop-out operation: up to 100% duty cycle selectable low noise/lo w consumption mode at light load power good signal 1% output voltage accuracy current-mode control 600 khz switching frequency externally synchronizable from 500 khz to 1.4 mhz ovp short circuit protection applications battery-powered equipment portable instruments cellular phones pdas and hand held terminals dsc gps description the device is dc-dc monolithic regulator specifically designed to provide extremely high efficiency. l6926 supply voltage can be as low as 2 v allowing its use in single li-ion cell supplied applications. output voltage can be selected by an external divider down to 0.6 v. duty cycle can saturate to 100% allowing low drop-out operation. the device is based on a 600 khz fixed- frequency, current mode-architecture. low consumption mode operation can be selected at light load conditions, allo wing switching losses to be reduced. l6926 is externally synchronizable with a clock which makes it useful in noise- sensitive applications. other features like power- good, overvoltage protection, short-circuit protection and thermal shutdown (150 c) are also present. vfqfpn8 msop8 (3x3x1.0 mm) figure 1. application test circuit l 6.8 h sync lx vfb c1 10 f 6.3v c2 220pf c4 10 f 6.3v r2 200k r3 500k r1 100k v in =2v to 5.5v v out =1.8v v cc run comp gnd pgood d01in1305 7 6 1 8 3 5 24 www.st.com
contents l6926 2/16 doc id 9302 rev 9 contents 1 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 operation description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1.1 low consumption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.2 low noise mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.1.3 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.3 slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.4 loop stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 additional features and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 dropout operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 pgood (power good output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.3 adjustable output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 ovp (overvoltage protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.5 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
l6926 pin settings doc id 9302 rev 9 3/16 1 pin settings figure 2. pin connection (top view) table 1. pin description pin n name description 1run shutdown input. when connected to a low level (lower than 0.4 v) the device stops working. when high (higher than 1.3 v) the device is enabled. 2comp error amplifier output. a compensation netw ork has to be connected to this pin. usually a 220 pf capacitor is enough to guarantee the loop stability. 3vfb error amplifier inverting input. the output voltage can be adjusted from 0.6 v up to the input voltage by connecting this pin to an external resistor divider. 4 gnd ground. 5lx switch output node. this pin is internally connected to the drain of the internal switches. 6v cc input voltage. the start up input voltage is 2.2 v (typ) while the operating input voltage range is from 2 v to 5.5 v. an internal uvlo circuit realizes a 100 mv (typ.) hysteresis. 7 sync operating mode selector input. when high (higher than 1.3 v) the low consumption mode is selected. when lo w (lower than 0.5 v) the low noise mode is selected. if connected with an appropriate external synchronization signal (from 500 khz up to 1.4 mhz) the internal synchronization circuit is activated and the device works at the same switching frequency. 8 pgood power good comparator output. it is an open drain output. a pull-up resistor should be connected between pgood and v out (or v cc depending on the requirements). the pin is forced low wh en the output voltage is lower than 90% of the regulated output voltage and goes high when the output voltage is greater than 90% of the regulated out put voltage. if not used the pin can be left floating. run comp vfb gnd 1 3 2 4lx v cc sync pgood 8 7 6 5 d01in1239amod
maximum ratings l6926 4/16 doc id 9302 rev 9 2 maximum ratings table 2. absolute maximum ratings symbol parameter value unit v 6 input voltage -0.3 to 6 v v 5 output switching voltage -1 to v cc v v 1 shutdown -0.3 to v cc v v 3 feedback voltage -0.3 to v cc v v 2 error amplifier output voltage -0.3 to v cc v v 8 pgood -0.3 to v cc v v 7 synchronization mode selector -0.3 to v cc v p tot power dissipation at t a = 70 c0.45w t j junction operating temperature range -40 to 150 c t stg storage temperature range -65 to 150 c lx pin maximum withstanding volt age range test condition: cdf-aec-q100-002- ?human body model? acceptance criteria: ?normal performance? 1000 v other pins 2000 v table 3. thermal data symbol parameter value unit r thja maximum thermal resistance junction-ambient for msop8 180 c/w maximum thermal resistance junction-ambient for vfqfpn8 56 c/w
l6926 electrical characteristics doc id 9302 rev 9 5/16 3 electrical characteristics t j = 25 c, v in = 3.6 v unless otherwise specified. table 4. electrical characteristics (1) symbol parameter test condition min. typ. max. unit v cc operating input voltage after turn on (1) 25.5v v cc on turn on threshold 2.2 v v cc off turn off threshold 2 v v cc hys hysteresis 100 mv r p high side ron v cc = 3.6 v, i lx =100 ma 240 300 m (1) 400 r n low side ron v cc = 3.6 v, i lx =100 ma 215 300 m (1) 400 i lim peak current limit v cc = 3.6 v 11.21.5 a (1) 0.85 1.65 valley current limit v cc = 3.6 v 11.41.7 a (1) 0.9 1.85 v out output voltage range v fb v cc v f osc oscillator frequency 450 600 700 khz (1) 400 600 800 f sync sync mode clock (2) 500 1400 khz dc characteristics i q quiescent current (low noise mode) v sync = 0 v, no load, v fb > 0.6 v 200 300 a v sync = 0 v, no load, v fb > 0.6 v (1) 300 quiescent current (low consumption mode) v sync = v cc , no load, v fb > 0.6 v (1) 25 50 a i sh shutdown current run to gnd, v cc = 5.5 v 0.2 a i lx lx leakage current (2) run to gnd, v lx = 5.5 v, v cc = 5.5 v 1a run to gnd, v lx = 0v, v cc = 5.5 v 1a error amplifier characteristics v fb voltage feedback 0.593 0.600 0.607 v (1) 0.590 0.600 0.610 v i fb feedback input current (2) v fb = 0.6 v 25 na
electrical characteristics l6926 6/16 doc id 9302 rev 9 symbol parameter test condition min. typ. max. unit run v run_h run threshold high 1.3 v v run_l run threshold low 0.4 v i run run input current (2) 25 na sync/mode function v sync_h sync mode threshold high 1.3 v v sync_l sync mode threshold low 0.5 v pgood section v pgood power good threshold v out = v fb 90 %v out v pgood power good hysteresis v out = v fb 4%v out v pgood(low) power good low voltage run to gnd 0.4 v i lk-pgood power good leakage current (2) v pgood = 3.6 v 50 na protections hovp hard overvoltage threshold v out = v fb 10 %v out 1. specification referred to t j from -40 c to +125 c. specific ation over the -40 to +125 c t j temperature range are assured by design, characterization and statistical correlation 2. guaranteed by design table 4. electrical characteristics (1) (continued)
l6926 operation description doc id 9302 rev 9 7/16 4 operation description the main loop uses slope compensated pwm current mode architecture. each cycle the high side mosfet is turned on, triggered by the oscillator, so that the current flowing through it (the same as the inductor current) increases. when this current reaches the threshold (set by the output of the error amplifier e/a), the peak current limit comparator peak_cl turns off the high side mosfet and turn s on the low side one until the next clock cycle begins or the current flowing through it goes down to zero (zero crossing comparator). the pe ak inductor curren t required to trigger peak_ cl depends on the slope compensation signal and on the output of the error amplifier. in particular, the error amplifier output depends on the v fb pin voltage. when the output current increases, the output capacitor is discharged and so the v fb pin decreases. this produces increase of the error amplifier output, so allowing a higher value for the peak inductor current. for the same reason, when due to a load transient the output current decreases, the error amplifier output goes low, so reducing the peak inductor current to meet the new load requirements. the slope compensation signal allows the loop stability also in high duty cycle conditions (see related section). figure 3. device block diagram 4.1 modes of operation depending on the sync pin value the device can operate in low consumption or low noise mode. if the sync pin is high (higher than 1.3 v) the low consumption mode is selected while the low noise mode is selected if the sync pin is low (lower than 0.5 v). vcc sync com p p good gnd driver gn d gn d gnd peak cl valley cl vcc zero crossing loop control oscillator low noise/ consum ption lx ovp v ref fb e/a p good power p mos power n mos sense p mos sense n mos vcc 0.6v v ref 0.9v sl op e run vcc sync com p p good gnd driver gn d gn d gnd peak cl valley cl vcc zero crossing loop control oscillator low noise/ consum ption lx ovp v ref fb e/a p good power p mos power n mos sense p mos sense n mos vcc 0.6v v ref 0.9v sl op e run
operation description l6926 8/16 doc id 9302 rev 9 4.1.1 low consumption mode in this mode of operation, at light load, the device operates discontinuously based on the comp pin voltage, in order to keep the efficiency very high also in these conditions. while the device is not switching the load discharges the output capacitor and the output voltage goes down. when the feedback voltage goes lower than the internal reference, the comp pin voltage increases and when an internal threshold is reached, the device starts to switch. in these conditions the peak current limit is set approximately in the range of 200 ma - 400 ma, depending on the slope compensation (see related section). once the device starts to switch the output capacitor is recharged. the feedback pin increases and, when it reaches a value slightly higher than the reference voltage, the output of the error amplifier goes down until a clamp is activated. at this point, the device stops to switch. in this phase, most of the internal circuitries are off, so reducing the device consumption down to a typical value of 25 a. 4.1.2 low noise mode if for noise reasons, the very low frequencies of the low consumption mode are undesirable, the low noise mode can be selected. in low noise mode, the efficiency is a little bit lower compared with the low consumption mode in very light load conditions but for medium-high load currents the efficiency values are very similar. basically, the device switches with its internal free running frequency of 600 khz. obviously, in very light load conditions, the device could skip some cycles in order to keep the output voltage in regulation. 4.1.3 synchronization the device can also be synchronized with an external signal from 500 khz up to 1.4 mhz. in this case the low noise mode is automatica lly selected. the device will eventually skip some cycles in very light load conditions. the internal synchronization circuit is inhibited in short-circuit and overvoltage conditions in order to keep the protections effective (see relative sections). 4.2 short circuit protection during the device operation, the inductor current increases during the high side turn on phase and decrease during the high side turn off phase based on the following equations: equation 1 equation 2 in strong overcurrent or short-circuit conditions the v out can be very close to zero. in this case i on increases and i off decreases. when the inductor peak current reaches the i on v in v out ? () l ---------------------------------- t on ? = i off v out () l ------------------- t off ? =
l6926 operation description doc id 9302 rev 9 9/16 current limit, the high side mosfet turns off and so the t on is reduced down to the minimum value (250 ns typ.) in order to reduce as much as possible i on . anyway, if v out is low enough it can be that the inductor peak current further increases because during the t off the current decays very slowly. due to this reason a second protection that fixes the maximum inductor valley current has been introduced. this protection doesn't allow the high side mosfet to turn on if the current flowing through the inductor is higher that a specified threshold (valley current limit). basically the t off is increased as much as required to bring the inductor current down to this threshold. so, the maximum peak current in worst case conditions will be: equation 3 where ipeak is the valley curren t limit (1.4 a typ.) and t on_min is the minimum t on of the high side mosfet. 4.3 slope compensation in current mode architectures, when the duty cycle of the application is higher than approximately 50%, a pulse-by-p ulse instability (the so calle d sub harmonic oscillation) can occur. to allow loop stability also in these conditio ns a slope compensation is present. this is realized by reducing the current flowing through the inductor necessary to trigger the comp comparator (with a fixed value for the comp pin voltage). with a given duty cycle higher than 50%, the stability problem is particularly present with an higher input voltage (due to the increased current ripple across the inductor), so the slope compensation effect increases as the input voltage increases. from an application point of view, the final effect is that the peak current limit depends both on the duty cycle (if higher than approximately 40%) and on the input voltage. 4.4 loop stability since the device is realized wit h a current mode architecture, th e loop stability is usually not a big issue. for most of the application a 220 pf connected between the comp pin and ground is enough to g uarantee the stability. in case very low esr capacitors are used for the output filter, such as multilayer ceramic capacitors, the zero introduced by the capacitor itself can shift at very high frequency and the transient loop response could be affected. adding a series resistor to the 220 pf capacitor can solve this problem. the right value for the resistor (in the range of 50 k) can be determined by checking the load transient response of the device. basically, the output voltage has to be checked at the scope after the load steps requ ired by the application. in ca se of stability problems, the output voltage could oscillates before to r each the regulated valu e after a load step. i peak i valley v in l -------- - t on_min ? + =
additional features and protections l6926 10/16 doc id 9302 rev 9 5 additional features and protections 5.1 dropout operation the li-ion battery voltage ranges from approximately 3 v and 4.1 v - 4.2 v (depending on the anode material). in case the regulated output voltage is from 2.5 v and 3.3 v, it can be that, close to the end of the battery life, the battery voltage goes down to the regulated one. in this case the device stops to switch, working at 100% of duty cycle, so minimizing the dropout voltage and the device losses. 5.2 pgood (power good output) a power good output signal is available. the v fb pin is internally connected to a comparator with a threshold set at 90% of the of reference voltage (0.6 v). since the output voltage is connected to the v fb pin by a resistor divider, when the output voltage goes lower than the regulated value, the v fb pin voltage goes lower than 90% of the internal reference value. the internal comparator is triggered and the pgood pin is pulled down. the pin is an open drain output and so, a pull up resistor should be connected to him. if the feature is not required, the pin can be left floating. 5.3 adjustable output voltage the output voltage can be adjusted by an external resistor divider from a minimum value of 0.6v up to the input voltage. the output voltage value is given by: equation 4 5.4 ovp (overvoltage protection) the device has an internal overvoltage protection circuit to protect the load. if the voltage at the feedback pin goes higher than an internal threshold set 10% (typ) higher than the reference voltage, the low side power mosfet is turned on until the feedback voltage goes lower than the reference one. during the overvoltage circuit intervention, the zero crossing comparator is disabled so that the device is also able to sink current. 5.5 thermal shutdown the device has also a thermal shutdown protection activated when the junction temperature reaches 150 c. in this case both the high side mosfet and the low side one are turned off. once the junction temperature goes back lower than 95 c, the device restarts the normal operation. v out 0.6 1 r 2 r 1 ------ - + ?? ?? ? =
l6926 package mechanical data doc id 9302 rev 9 11/16 6 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. table 5. msop8 mechanical data dim. mm. min. typ. max. a 1.10 a1 0 0.15 a2 0.75 0.85 0.95 b 0.22 0.40 c 0.08 0.23 d (1) 1. dimension ?d? and ?e1? does not in clude mold flash or protrusions. mold flash or protrusions shall not exceed 0.15 mm per side. 2.80 3.00 3.20 e 4.65 4.90 5.15 e1 (1) 2.80 3.00 3.10 e0.65 l 0.40 0.60 0.80 l1 0.95 l2 0.25 k0 8 ccc 0.10
package mechanical data l6926 12/16 doc id 9302 rev 9 figure 4. msop8 package dimensions 7113595_b
l6926 package mechanical data doc id 9302 rev 9 13/16 outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 0.80 0.90 1.00 0.0315 0.0354 0.0394 a1 0.02 0.05 0.0008 0.0020 a2 0.70 0.0276 a3 0.20 0.0079 b 0.18 0.23 0.30 0.0071 0.0091 0.0118 d 3.00 0.1181 d2 2.23 2.38 2.48 0.0878 0.0937 0.0976 e 3.00 0.1181 e2 1.49 1.64 1.74 0.0587 0.0646 0.0685 e 0.50 0.0197 l 0.30 0.40 0.50 0.0118 0.0157 0.0197 ddd 0.08 0.0031 vfqfpn8 (3x3x1.0 8mm) v ery thin f ine pitch q uad p ackages n o lead 7426334 b
order codes l6926 14/16 doc id 9302 rev 9 7 order codes table 6. order codes order codes packages packaging l6926 msop8 tube L6926013TR msop8 tape and reel l6926q1 vfqfpn8 tube l6926q1tr vfqfpn8 tape and reel
l6926 revision history doc id 9302 rev 9 15/16 8 revision history table 7. document revision history date revision changes jan-2004 2 first issue in edocs. sep-2004 3 changed the style look and feel. add. new package vfson8. add. v8 and v7 parameter in the table 2 - absolute maximum ratings. nov-2004 4 update order codes sep-2005 5 updated table. 5 electrical characteristics. nov-2005 6 added vfqfpn8 package and new part numbers. 27-oct-2006 7 added r thja for vfqfpn8 in table 3. 16-sep-2008 8 vfson8 package no longer available 11-apr-2011 9 updated msop8 package mechanical data table 5 on page 11 and figure 4 on page 12 .
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